![I'm trying implement a 8x1 mux using 2 4x1 and 1 2x1 muxes, I have written some code but the schematic doesn't quite represent it correctly. I'm fairly new to verilog, any I'm trying implement a 8x1 mux using 2 4x1 and 1 2x1 muxes, I have written some code but the schematic doesn't quite represent it correctly. I'm fairly new to verilog, any](https://i.redd.it/5rmy2vswvrm81.png)
I'm trying implement a 8x1 mux using 2 4x1 and 1 2x1 muxes, I have written some code but the schematic doesn't quite represent it correctly. I'm fairly new to verilog, any
![What is multiplexer tree? Construct 32:1 multiplexer using 8:1 multiplexer only. Explain how the logic on particular data line is steered to the output in this design with example. What is multiplexer tree? Construct 32:1 multiplexer using 8:1 multiplexer only. Explain how the logic on particular data line is steered to the output in this design with example.](https://i.imgur.com/sim0vG2.png)
What is multiplexer tree? Construct 32:1 multiplexer using 8:1 multiplexer only. Explain how the logic on particular data line is steered to the output in this design with example.
![making 16x1 multiplexer by using two 8x1 multiplexer and one 2x1 - Electrical Engineering Stack Exchange making 16x1 multiplexer by using two 8x1 multiplexer and one 2x1 - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/p4Fk9.png)